Ms. Swati
Designation: Ad-Hoc Assistant Professor
Mrs. Swati K is an adhoc-Assistant Professor at Adani University. She is pursuing her Ph.D. in the Department of Electronics Engineering at Sardar Vallabhbhai National Institute of Technology (SVNIT), Surat. She completed her M.Tech. from Cochin University of Science and Technology (CUSAT), Kochi, and her B.E. from RNS Institute of Technology (RNSIT), Bengaluru.
Her research focuses on Edge AI, Deep Learning, and FPGA-based hardware acceleration for efficient deployment of deep learning models on resource-constrained edge devices. Her research interests include Artificial Intelligence, Computer Vision, Embedded Systems, VLSI design, and hardware-software co-design. She has worked on designing and optimizing CNN accelerators using techniques such as quantization, high-level synthesis, and low-power hardware architecture. She has also been actively involved in teaching, mentoring, and academic activities in the areas of Artificial Intelligence and Machine Learning.
| Degree | Institute | Specialization and Year | GPA / %age |
|---|---|---|---|
| SSLC (10th) | DAV Khabra | 2010 | 9.4 (CGPA) |
| HSC (12th) | JVM Shayamali, Ranchi | PCM, 2012 | 84.6% |
| B.E. | RNSIT, Bangalore | ECE, 2016 | 73.2% |
| M.Tech | DoE, CUSAT, Kochi | ECE, 2020 | 9.03 (CGPA) |
| Ph.D. | DoECE, SVNIT, Surat | Edge AI, Thesis Submitted | — |
- Software Developer, MetricStream InfoTech Pvt. Ltd., Bangalore, From: 15th June, 2016 to 17th November, 2017
- AI Research Intern, ITC InfoTech Pvt. Ltd., Bangalore, From: 15th May, 2019 to 30th April, 2020
- Full-Time PhD Research Scholar, DoECE, SVNIT, Surat, From: 20th September, 2020 to 23rd December, 2025
- Teaching Assistant, DoAI, SVNIT, Surat, From: 24th December, 2025 to 1st June, 2026
Edge AI and Embedded Intelligence, Deep Learning Acceleration, FPGA-based Hardware Design, Hardware-Software Co-design, Low-Power Computing Architectures, and Efficient Deployment of AI Models on Resource-Constrained Devices.
- Swati, S. Banarjee and P. Engineer, “A Template-Based Methodology for Efficient DNNs Inference on FPGA Devices With HW-SW Co-Design,” in IEEE Embedded Systems Letters, doi: 10.1109/LES.2025.3538159
- Swati, S., Kawa, S. D., Kamble, S., Desai, D., Karelia, P. H., & Engineer, P. (2024), “An Efficient Deep Learning Based License Plate Recognition for Smart Cities”. Electronic Letters on Computer Vision and Image Analysis, 23(2), 50–64. https://doi.org/10.5565/rev/elcvia.1917
- Swati, Ranajoy Sadhukhan, Mitul S. Nagar, Hiren Mewada, and Pinalkumar Engineer, “A Memory Efficient Run-time Re-configurable Convolution IP Core for Deep Neural Networks Inference on FPGA Devices”, 9th IEEE International Symposium on Smart Electronic Systems (iSES-2023) Dec-2023., pp. 409-412, doi: 10.1109/iSES58672.2023.00091
- Mitul S. Nagar, Vivek Chauhan, Karnav M. Chinchavde, Swati, Sat Patel, and Pinalkumar Engineer, “Energy-efficient Acceleration of Deep Learning based Facial Recognition on RISC-V Processor”, International Conference on Intelligent Systems and Embedded Design (ISED-2023) Dec-2023, DOI: 10.1109/ISED 59382.2023.10444594.
- Swati, V. N. Kumar, S. Dinesh Kawa and P. Engineer, ”An Efficient Object Tracking on Edge Devices with Quantized Siamese Networks,” 2025 Devices for Integrated Circuit (DevIC), Kalyani, India, 2025, pp. 604-609, doi: 10.1109/DevIC63749.2025.11012629
- Swati, Shubh Kawa, Rinkesh Patel, Amin M Amrish, Mitul Nagar and Pinalkumar Engineer, “Exploring Quantization Approaches for Optimized Training and Inference for Edge AI Applications,” 2025 11th International Conference on Communication and Signal Processing (ICCSP), Melmaruvathur, India, 2025, pp. 1362-1367, doi: 10.1109/ICCSP64183.2025.11088699.
- Swati, H. Parmar and P. Engineer, ”Edge AI Acceleration on Ultra96 SoC: Rapid Model-to-FPGA Hardware Mapping Using NNgen,” 2025 13th International Conference on Intelligent Systems and Embedded Design (ISED), Raipur, India, 2025, pp. 1025-1030, doi: 10.1109/ISED67359.2025.11405159.
- Swati, Verma, D., Prajapati, J., Engineer, P. (2024). “Quantization Effects on a Convolutional Layer of a Deep Neural Network”. https://doi.org/10.1007/978-981-99-5180-2 32
- Swati and Pinalkumar Engineer. “Efficient FPGA-Based Convolution Operations: Application-Centric Design and Optimization”. International Conference on Women Researchers in Electronics and Computing on sustainable development goals 2025 (WREC 25), Accepted and presented. To be published in Lecture Notes in Electrical Engineering, Springer.
- Swati, Jay Modi, Disha Lad and Pinalkumar Engineer, “Efficient License Plate Detection and Recognition with FPGA-Based Hardware-Software Co-Design”, The 29th International Symposium on VLSI Design and Test (VDAT-2025). Accepted and presented. To be published in Lecture Notes in Computer Science, Springer.
- Swati, Shubham Kamble and Pinalkumar Engineer, “An Effcient Hardware-Software Co-Design for Dense Layer Acceleration on FPGA Using Reusable MAC Arrays: SDK vs Overlay Approaches”, The 29th International Symposium on VLSI Design and Test (VDAT-2025). Accepted and presented. To be published in Lecture Notes in Computer Science, Springer.
- AI-Based Digital Image Processing Device for Object Detection and Recognition, Design Registration No. 6508347, UK Intellectual Property Office, 2026.
- Hardware implementation of a deep learning-based automatic license plate recognition (ALPR) system, Sponsored research project supported under IGNITION 3.0 – SSIP 2.0, ASHINE, SVNIT, Surat (2023-24). Approval No.: SVNIT/ASHINE/SSIP 2.0/IGNITION 3.0/2023-24/113. (Role: Lead Innovator)
- Attended National level FDP on Generative & Agentic AI- Tools & Demo by DoCSE, SVNIT and Pantech Solutions (India) Pvt. Ltd.
- NPTEL Certification for the course “Deep Learning for Visual Computing”, IIT Kharagpur
